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dc.contributor.author | Shawky, Ahmed | |
dc.contributor.author | Aly, Mokhtar | |
dc.contributor.author | Alhosaini, Waleed | |
dc.contributor.author | Ahmed, Emad M. | |
dc.contributor.author | Mohamed, Emad A. | |
dc.contributor.author | Alshahir, Ahmed | |
dc.date.accessioned | 2024-09-26T00:53:47Z | |
dc.date.available | 2024-09-26T00:53:47Z | |
dc.date.issued | 2024 | |
dc.identifier.issn | 2169-3536 | |
dc.identifier.other | Mendeley: 4af48267-6675-3104-9485-bba4a36a38bb | |
dc.identifier.uri | https://repositorio.uss.cl/handle/uss/13969 | |
dc.description | Publisher Copyright: Authors | |
dc.description.abstract | Single-stage differential mode inverters (DMI) have been extensively utilized in three-phase grid-connected systems due to several advantages, such as few semiconductor devices resulting from their simple and modular configuration. Nevertheless, the modulation and control strategy require further enhancement to enable more efficient power conversion across various operations. Therefore, this paper introduces a detailed analytical model of the SEPIC-DMI, leading to the development of a hybrid discontinuous modulation scheme pulse width modulation (DMS-PWM), which incorporates zero voltage switching (ZVS), denoted as Hybrid DMS-ZVS-PWM approach. In the proposed strategy, the duty cycle of SEPIC-DMI is zero for one-third of the grid frequency cycle, which leads to minimizing conduction and switching power losses. Moreover, the voltage stress on the components is significantly reduced due to DMS-PWM. For ZVS, a simplified active-clamp circuit is proposed and designated using a single switch and two small capacitors. The proposed active-clamp circuit is integrated into the SEPIC-DMI to verify SEPIC power switches’ ZVS and zero current switching (ZCS). The ZVS/ZCS improves the inverter efficiency by major minimization in power losses. The mathematical derivations and performance measurements (simulation and experiment) are provided to show the superiority of the proposed hybrid DMS-ZVS-PWM method. The peak efficiency of SEPIC-DMI is enhanced from 90% to 94%, and the voltage stress is curtailed in all components with 13%. | en |
dc.description.abstract | Single-stage differential mode inverters (DMI) have been extensively utilized in three-phase grid-connected systems due to several advantages, such as few semiconductor devices resulting from their simple and modular configuration. Nevertheless, the modulation and control strategy require further enhancement to enable more efficient power conversion across various operations. Therefore, this paper introduces a detailed analytical model of the SEPIC-DMI, leading to the development of a hybrid discontinuous modulation scheme pulse width modulation (DMS-PWM), which incorporates zero voltage switching (ZVS), denoted as Hybrid DMS-ZVS-PWM approach. In the proposed strategy, the duty cycle of SEPIC-DMI is zero for one-third of the grid frequency cycle, which leads to minimizing conduction and switching power losses. Moreover, the voltage stress on the components is significantly reduced due to DMS-PWM. For ZVS, a simplified active-clamp circuit is proposed and designated using a single switch and two small capacitors. The proposed active-clamp circuit is integrated into the SEPIC-DMI to verify SEPIC power switches’ ZVS and zero current switching (ZCS). The ZVS/ZCS improves the inverter efficiency by major minimization in power losses. The mathematical derivations and performance measurements (simulation and experiment) are provided to show the superiority of the proposed hybrid DMS-ZVS-PWM method. The peak efficiency of SEPIC-DMI is enhanced from 90% to 94%, and the voltage stress is curtailed in all components with 13%. | es |
dc.language.iso | eng | |
dc.relation.ispartof | vol. 12 Issue: Pages: 109832-109846 | |
dc.source | IEEE Access | |
dc.title | Hybrid DMS-ZVS-PWM With In-Depth Mathematical Model for Boosting Efficiency of Grid-Connected SEPIC Differential Mode Inverter | en |
dc.type | Artículo | |
dc.identifier.doi | 10.1109/ACCESS.2024.3437768 | |
dc.publisher.department | Facultad de Ingeniería, Arquitectura y Diseño | |
dc.publisher.department | Facultad de Ingeniería y Tecnología |
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